LibXenon
Bare-metal Xbox 360 homebrew library
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Go to the source code of this file.
Data Structures | |
struct | ehci_caps |
struct | ehci_regs |
struct | ehci_dbg_port |
Macros | |
#define | HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */ |
#define | HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */ |
#define | HCS_DEBUG_PORT(p) (((p)>>20)&0xf) /* bits 23:20, debug port? */ |
#define | HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */ |
#define | HCS_N_CC(p) (((p)>>12)&0xf) /* bits 15:12, #companion HCs */ |
#define | HCS_N_PCC(p) (((p)>>8)&0xf) /* bits 11:8, ports per CC */ |
#define | HCS_PORTROUTED(p) ((p)&(1 << 7)) /* true: port routing */ |
#define | HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */ |
#define | HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */ |
#define | HCC_EXT_CAPS(p) (((p)>>8)&0xff) /* for pci extended caps */ |
#define | HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */ |
#define | HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */ |
#define | HCC_CANPARK(p) ((p)&(1 << 2)) /* true: can park on async qh */ |
#define | HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/ |
#define | HCC_64BIT_ADDR(p) ((p)&(1)) /* true: can use 64-bit addr */ |
#define | CMD_PARK (1<<11) /* enable "park" on async qh */ |
#define | CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */ |
#define | CMD_LRESET (1<<7) /* partial reset (no ports, etc) */ |
#define | CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */ |
#define | CMD_ASE (1<<5) /* async schedule enable */ |
#define | CMD_PSE (1<<4) /* periodic schedule enable */ |
#define | CMD_RESET (1<<1) /* reset HC not bus */ |
#define | CMD_RUN (1<<0) /* start/stop HC */ |
#define | STS_ASS (1<<15) /* Async Schedule Status */ |
#define | STS_PSS (1<<14) /* Periodic Schedule Status */ |
#define | STS_RECL (1<<13) /* Reclamation */ |
#define | STS_HALT (1<<12) /* Not running (any reason) */ |
#define | STS_IAA (1<<5) /* Interrupted on async advance */ |
#define | STS_FATAL (1<<4) /* such as some PCI access errors */ |
#define | STS_FLR (1<<3) /* frame list rolled over */ |
#define | STS_PCD (1<<2) /* port change detect */ |
#define | STS_ERR (1<<1) /* "error" completion (overflow, ...) */ |
#define | STS_INT (1<<0) /* "normal" completion (short, ...) */ |
#define | FLAG_CF (1<<0) /* true: we'll support "high speed" */ |
#define | PORT_WKOC_E (1<<22) /* wake on overcurrent (enable) */ |
#define | PORT_WKDISC_E (1<<21) /* wake on disconnect (enable) */ |
#define | PORT_WKCONN_E (1<<20) /* wake on connect (enable) */ |
#define | PORT_LED_OFF (0<<14) |
#define | PORT_LED_AMBER (1<<14) |
#define | PORT_LED_GREEN (2<<14) |
#define | PORT_LED_MASK (3<<14) |
#define | PORT_OWNER (1<<13) /* true: companion hc owns this port */ |
#define | PORT_POWER (1<<12) /* true: has power (see PPC) */ |
#define | PORT_USB11(x) (((x)&(3<<10)) == (1<<10)) /* USB 1.1 device */ |
#define | PORT_RESET (1<<8) /* reset port */ |
#define | PORT_SUSPEND (1<<7) /* suspend port */ |
#define | PORT_RESUME (1<<6) /* resume it */ |
#define | PORT_OCC (1<<5) /* over current change */ |
#define | PORT_OC (1<<4) /* over current active */ |
#define | PORT_PEC (1<<3) /* port enable change */ |
#define | PORT_PE (1<<2) /* port enable */ |
#define | PORT_CSC (1<<1) /* connect status change */ |
#define | PORT_CONNECT (1<<0) /* device connected */ |
#define | PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC) |
#define | USBMODE 0x68 /* USB Device mode */ |
#define | USBMODE_SDIS (1<<3) /* Stream disable */ |
#define | USBMODE_BE (1<<2) /* BE/LE endianness select */ |
#define | USBMODE_CM_HC (3<<0) /* host controller mode */ |
#define | USBMODE_CM_IDLE (0<<0) /* idle state */ |
#define | DBGP_OWNER (1<<30) |
#define | DBGP_ENABLED (1<<28) |
#define | DBGP_DONE (1<<16) |
#define | DBGP_INUSE (1<<10) |
#define | DBGP_ERRCODE(x) (((x)>>7)&0x07) |
#define | DBGP_ERR_BAD 1 |
#define | DBGP_ERR_SIGNAL 2 |
#define | DBGP_ERROR (1<<6) |
#define | DBGP_GO (1<<5) |
#define | DBGP_OUT (1<<4) |
#define | DBGP_LEN(x) (((x)>>0)&0x0f) |
#define | DBGP_PID_GET(x) (((x)>>16)&0xff) |
#define | DBGP_PID_SET(data, tok) (((data)<<8)|(tok)) |
#define | DBGP_EPADDR(dev, ep) (((dev)<<8)|(ep)) |
Functions | |
struct ehci_caps | __attribute__ ((packed)) |
Variables | |
u32 | hc_capbase |
u32 | hcs_params |
u32 | hcc_params |
u8 | portroute [8] |
u32 | command |
u32 | status |
u32 | intr_enable |
u32 | frame_index |
u32 | segment |
u32 | frame_list |
u32 | async_next |
u32 | reserved [9] |
u32 | configured_flag |
u32 | port_status [0] |
u32 | control |
u32 | pids |
u32 | data03 |
u32 | data47 |
u32 | address |
#define CMD_ASE (1<<5) /* async schedule enable */ |
Definition at line 8 of file ehci_defs.h.
#define CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */ |
Definition at line 7 of file ehci_defs.h.
#define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */ |
Definition at line 6 of file ehci_defs.h.
#define CMD_PARK (1<<11) /* enable "park" on async qh */ |
Definition at line 4 of file ehci_defs.h.
Definition at line 5 of file ehci_defs.h.
#define CMD_PSE (1<<4) /* periodic schedule enable */ |
Definition at line 9 of file ehci_defs.h.
#define CMD_RESET (1<<1) /* reset HC not bus */ |
Definition at line 11 of file ehci_defs.h.
#define CMD_RUN (1<<0) /* start/stop HC */ |
Definition at line 12 of file ehci_defs.h.
#define DBGP_DONE (1<<16) |
Definition at line 3 of file ehci_defs.h.
#define DBGP_ENABLED (1<<28) |
Definition at line 2 of file ehci_defs.h.
#define DBGP_EPADDR | ( | dev, | |
ep | |||
) | (((dev)<<8)|(ep)) |
Definition at line 18 of file ehci_defs.h.
#define DBGP_ERR_BAD 1 |
Definition at line 6 of file ehci_defs.h.
#define DBGP_ERR_SIGNAL 2 |
Definition at line 7 of file ehci_defs.h.
#define DBGP_ERRCODE | ( | x | ) | (((x)>>7)&0x07) |
Definition at line 5 of file ehci_defs.h.
#define DBGP_ERROR (1<<6) |
Definition at line 8 of file ehci_defs.h.
#define DBGP_GO (1<<5) |
Definition at line 9 of file ehci_defs.h.
#define DBGP_INUSE (1<<10) |
Definition at line 4 of file ehci_defs.h.
#define DBGP_LEN | ( | x | ) | (((x)>>0)&0x0f) |
Definition at line 11 of file ehci_defs.h.
#define DBGP_OUT (1<<4) |
Definition at line 10 of file ehci_defs.h.
#define DBGP_OWNER (1<<30) |
Definition at line 1 of file ehci_defs.h.
#define DBGP_PID_GET | ( | x | ) | (((x)>>16)&0xff) |
Definition at line 13 of file ehci_defs.h.
Definition at line 14 of file ehci_defs.h.
#define FLAG_CF (1<<0) /* true: we'll support "high speed" */ |
Definition at line 45 of file ehci_defs.h.
#define HC_LENGTH | ( | p | ) | (((p)>>00)&0x00ff) /* bits 7:0 */ |
Definition at line 4 of file ehci_defs.h.
#define HC_VERSION | ( | p | ) | (((p)>>16)&0xffff) /* bits 31:16 */ |
Definition at line 5 of file ehci_defs.h.
#define HCC_64BIT_ADDR | ( | p | ) | ((p)&(1)) /* true: can use 64-bit addr */ |
Definition at line 21 of file ehci_defs.h.
#define HCC_CANPARK | ( | p | ) | ((p)&(1 << 2)) /* true: can park on async qh */ |
Definition at line 19 of file ehci_defs.h.
#define HCC_EXT_CAPS | ( | p | ) | (((p)>>8)&0xff) /* for pci extended caps */ |
Definition at line 16 of file ehci_defs.h.
#define HCC_ISOC_CACHE | ( | p | ) | ((p)&(1 << 7)) /* true: can cache isoc frame */ |
Definition at line 17 of file ehci_defs.h.
#define HCC_ISOC_THRES | ( | p | ) | (((p)>>4)&0x7) /* bits 6:4, uframes cached */ |
Definition at line 18 of file ehci_defs.h.
#define HCC_PGM_FRAMELISTLEN | ( | p | ) | ((p)&(1 << 1)) /* true: periodic_size changes*/ |
Definition at line 20 of file ehci_defs.h.
#define HCS_DEBUG_PORT | ( | p | ) | (((p)>>20)&0xf) /* bits 23:20, debug port? */ |
Definition at line 7 of file ehci_defs.h.
#define HCS_INDICATOR | ( | p | ) | ((p)&(1 << 16)) /* true: has port indicators */ |
Definition at line 8 of file ehci_defs.h.
#define HCS_N_CC | ( | p | ) | (((p)>>12)&0xf) /* bits 15:12, #companion HCs */ |
Definition at line 9 of file ehci_defs.h.
#define HCS_N_PCC | ( | p | ) | (((p)>>8)&0xf) /* bits 11:8, ports per CC */ |
Definition at line 10 of file ehci_defs.h.
#define HCS_N_PORTS | ( | p | ) | (((p)>>0)&0xf) /* bits 3:0, ports on HC */ |
Definition at line 13 of file ehci_defs.h.
#define HCS_PORTROUTED | ( | p | ) | ((p)&(1 << 7)) /* true: port routing */ |
Definition at line 11 of file ehci_defs.h.
#define HCS_PPC | ( | p | ) | ((p)&(1 << 4)) /* true: port power control */ |
Definition at line 12 of file ehci_defs.h.
#define PORT_CONNECT (1<<0) /* device connected */ |
Definition at line 71 of file ehci_defs.h.
#define PORT_CSC (1<<1) /* connect status change */ |
Definition at line 70 of file ehci_defs.h.
#define PORT_LED_AMBER (1<<14) |
Definition at line 55 of file ehci_defs.h.
#define PORT_LED_GREEN (2<<14) |
Definition at line 56 of file ehci_defs.h.
#define PORT_LED_MASK (3<<14) |
Definition at line 57 of file ehci_defs.h.
#define PORT_LED_OFF (0<<14) |
Definition at line 54 of file ehci_defs.h.
#define PORT_OC (1<<4) /* over current active */ |
Definition at line 67 of file ehci_defs.h.
#define PORT_OCC (1<<5) /* over current change */ |
Definition at line 66 of file ehci_defs.h.
#define PORT_OWNER (1<<13) /* true: companion hc owns this port */ |
Definition at line 58 of file ehci_defs.h.
#define PORT_PE (1<<2) /* port enable */ |
Definition at line 69 of file ehci_defs.h.
#define PORT_PEC (1<<3) /* port enable change */ |
Definition at line 68 of file ehci_defs.h.
#define PORT_POWER (1<<12) /* true: has power (see PPC) */ |
Definition at line 59 of file ehci_defs.h.
#define PORT_RESET (1<<8) /* reset port */ |
Definition at line 63 of file ehci_defs.h.
#define PORT_RESUME (1<<6) /* resume it */ |
Definition at line 65 of file ehci_defs.h.
Definition at line 72 of file ehci_defs.h.
#define PORT_SUSPEND (1<<7) /* suspend port */ |
Definition at line 64 of file ehci_defs.h.
#define PORT_USB11 | ( | x | ) | (((x)&(3<<10)) == (1<<10)) /* USB 1.1 device */ |
Definition at line 60 of file ehci_defs.h.
#define PORT_WKCONN_E (1<<20) /* wake on connect (enable) */ |
Definition at line 52 of file ehci_defs.h.
#define PORT_WKDISC_E (1<<21) /* wake on disconnect (enable) */ |
Definition at line 51 of file ehci_defs.h.
#define PORT_WKOC_E (1<<22) /* wake on overcurrent (enable) */ |
Definition at line 50 of file ehci_defs.h.
#define STS_ASS (1<<15) /* Async Schedule Status */ |
Definition at line 16 of file ehci_defs.h.
#define STS_ERR (1<<1) /* "error" completion (overflow, ...) */ |
Definition at line 26 of file ehci_defs.h.
#define STS_FATAL (1<<4) /* such as some PCI access errors */ |
Definition at line 23 of file ehci_defs.h.
#define STS_FLR (1<<3) /* frame list rolled over */ |
Definition at line 24 of file ehci_defs.h.
#define STS_HALT (1<<12) /* Not running (any reason) */ |
Definition at line 19 of file ehci_defs.h.
#define STS_IAA (1<<5) /* Interrupted on async advance */ |
Definition at line 22 of file ehci_defs.h.
#define STS_INT (1<<0) /* "normal" completion (short, ...) */ |
Definition at line 27 of file ehci_defs.h.
#define STS_PCD (1<<2) /* port change detect */ |
Definition at line 25 of file ehci_defs.h.
#define STS_PSS (1<<14) /* Periodic Schedule Status */ |
Definition at line 17 of file ehci_defs.h.
#define STS_RECL (1<<13) /* Reclamation */ |
Definition at line 18 of file ehci_defs.h.
#define USBMODE 0x68 /* USB Device mode */ |
Definition at line 129 of file ehci_defs.h.
#define USBMODE_BE (1<<2) /* BE/LE endianness select */ |
Definition at line 131 of file ehci_defs.h.
#define USBMODE_CM_HC (3<<0) /* host controller mode */ |
Definition at line 132 of file ehci_defs.h.
#define USBMODE_CM_IDLE (0<<0) /* idle state */ |
Definition at line 133 of file ehci_defs.h.
#define USBMODE_SDIS (1<<3) /* Stream disable */ |
Definition at line 130 of file ehci_defs.h.
struct ehci_caps __attribute__ | ( | (packed) | ) |
u32 address |
Definition at line 17 of file ehci_defs.h.
u32 async_next |
Definition at line 39 of file ehci_defs.h.
u32 command |
Definition at line 2 of file ehci_defs.h.
u32 configured_flag |
Definition at line 44 of file ehci_defs.h.
u32 control |
Definition at line 0 of file ehci_defs.h.
u32 data03 |
Definition at line 15 of file ehci_defs.h.
u32 data47 |
Definition at line 16 of file ehci_defs.h.
u32 frame_index |
Definition at line 33 of file ehci_defs.h.
u32 frame_list |
Definition at line 37 of file ehci_defs.h.
u32 hc_capbase |
Definition at line 3 of file ehci_defs.h.
u32 hcc_params |
Definition at line 15 of file ehci_defs.h.
u32 hcs_params |
Definition at line 6 of file ehci_defs.h.
u32 intr_enable |
Definition at line 30 of file ehci_defs.h.
u32 pids |
Definition at line 12 of file ehci_defs.h.
u32 port_status[0] |
Definition at line 48 of file ehci_defs.h.
u8 portroute[8] |
Definition at line 22 of file ehci_defs.h.
u32 reserved[9] |
Definition at line 41 of file ehci_defs.h.
u32 segment |
Definition at line 35 of file ehci_defs.h.
u32 status |
Definition at line 15 of file ehci_defs.h.